Syllabus
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Course Code: EC-306 Course Name: Verilog HDL |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Introduction: Introduction, conventional approach to digital design, VLSI design, ASIC design
flow, Role of HDL, Conventional Data flow, ASIC data flow, Verilog as HDL, Levels of Design
Description, Concurrency, Simulation and Synthesis, Functional Verification, System Tasks,
Programming Language Interface (PLI), Module, Simulation and Synthesis Tools, Test Benches. Language constructs and conventions: Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Memory, Operators, System Tasks. |
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| 2 | Gate level modelling: Introduction, AND Gate Primitive, Module Structure, Other Gate
Primitives, Illustrative Examples, Tri-State Gates, Array of Instances of Primitives, Additional
Examples, Design of Flip-flops with Gate Primitives, Delays, Strengths and Contention Resolution,
Net Types, Design of Basic Circuits. Behavioralmodelling: Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct, Always Construct, Examples, Assignments with Delays, Wait construct, Multiple Always Blocks, Designs at Behavioral Level, Blocking and Non-blocking Assignments, The case statement, Simulation Flow, if and ifelse constructs, assign-deassign construct, repeat construct, for loop, the disable construct, while loop, forever loop, parallel blocks, force-release construct, Event. |
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| 3 | Modelling at data flow level: Introduction, Continuous Assignment Structures, Delays and
Continuous Assignments, Assignment to Vectors, Operators, Additional Examples. Switch level modelling: Introduction, Basic Transistor Switches, CMOS Switch, Bi-directional Gates, Time Delays with Switch Primitives, Instantiations with Strengths and Delays, Strength Contention with Trireg Nets. |
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| 4 | Functions, tasks, and user defined primitives: Introduction, Function, Tasks, User- Defined
Primitives (UDP), FSM Design (Moore and Mealy Machines). System tasks, functions, and compiler directives: Introduction, Parameters, Path Delays, Module Parameters, System Tasks and Functions, File-Based Tasks and Functions, Compiler Directives, Hierarchical Access, General Observations. |
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