Syllabus
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Course Code: *DSEE-608 Course Name: DSEE6: Verilog and FPGA based System Design |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Digital logic design flow , Review of combinational circuits , Combinational building blocks: multiplexors, demultiplexers , decoders, encoders and adder circuits. Review of sequential circuit elements: flip-flop, latch and register. | |
| 2 | Finite state machines: Mealy and Moore. Other sequential circuits: shift registers and counters. FSMD (Finite State Machine with Datapath) : design and analysis. Microprogrammed control. Memory basics and timing. Programmable Logic devices | |
| 3 | Evolution of Programmable logic devices : PAL, PLA and GAL. CPLD and FPGA Architectures, Placement and routing, Logic cell structure, Programmable interconnects, Logic blocks and I/O Ports , Clock distribution in FPGA. Timing issues in FPGA design. Boundary scan. | |
| 4 | Verilog HDL: Introduction to HDL , Verilog primitive operators and structural Verilog Behavioral Verilog, Design verification. Modeling of combinational and sequential circuits (including FSM and FSMD) with Verilog Design examples in Verilog | |
