Syllabus
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Course Code: EL 23 Course Name: Verilog- Hardware Description Language |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Benefits of CAD, Integrated circuit design techniques, Hierarchical design, Design abstraction, Computer aided design, Concepts of CPLD, FPGA. Introduction to HDLs, Verilog and its capabilities, Hierarchical Modeling Concepts: Design Methodologies, Modules, Instances, Components of Simulation and Test Bench. Basic Concepts: Lexical Conventions, Data Types, System Tasks and Compiler Directives. Modules and Ports. |
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| 2 | Gate-Level Modeling: Gate Types, Gate Delays. Dataflow Modeling, Continuous Assignments, Delays, Expressions, Operators, and Operands, Operator Types, Switch-Level Modeling: Switch-Modeling Elements. |
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| 3 | Behavioral Modeling: Structured Procedures, Procedural Assignments, Timing Controls, Conditional Statements, Multiway Branching, Loops, Sequential and Parallel Blocks, Generate Blocks. Tasks and Functions. |
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| 4 | Timing and Delays, Types of Delay Models, Path Delay Modeling, Timing Checks, Delay Back-Annotation, User-Defined Primitives (brief), Programming Language Interface (brief), Logic Synthesis with Verilog, Synthesis Design Flow, Verification of Gate-Level Netlist. Verification Techniques (brief) : Traditional Verification Flow, Assertion Checking, Formal Verification |
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