Syllabus
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Course Code: MMVD 302 Course Name: Program Elective-II - Digital System Testing and Fault Sim |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Role of testing in VLSI Design flow, Testing at different levels of abstraction.
Functional Modeling at the logic Level, Functional Modeling at the Register Level, Structural Models, Level of Modeling. Types of Simulation, Compiled Simulation, Event-Driven Simulation, Delay Models. Basic of Test and role of HDLs in testing (Introduction only), Verilog HDL for Design and Test in combinational circuits and sequential circuits. |
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| 2 | Fault Modeling:- Fault Abstraction, Functional Faults, Structural Faults, Structural Gate Level Faults, Recognizing Faults, Stuck-Open Faults, Stuck-at-0 Faults, Stuck-at-1 Faults, Bridging Faults, State-Dependent Faults, Multiple Faults, Single Stuck-at-Structural Faults, Detecting Single Stuck-at Fault, Detecting Bridging Faults, Fault Collapsing, Dominance Fault Collapsing, Fault Simulation:-Gate-Level Fault Simulation. |
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| 3 | Testing for single step faults - Basic Issues, ATG algorithms for SSFs in Combinational Circuits: D, 9-V, PODEM Algorithms, Fault independent test generation, Sequential Circuit test generation. |
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| 4 | Design for Test, Testing Sequential and Combinational Circuits, Ad Hoc Design for Testability Techniques, Testability insertion - Controllability and Observability concept, Full Scan Insertion, Flip - Flop Structures, General Aspects of Compression Techniques, Ones-Count Compression, LFSR used as signature analyzer , Introduction to BIST and MBIST. |
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