Syllabus
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Course Code: MMVD 204 Course Name: Verilog - Hardware Description Language |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Verilog: Overview of Digital Design with Verilog HDL, Hierarchical Modeling, Basics of Verilog - Data Types, System Tasks and Compiler Directives, Modules and Ports, Gate Level Modeling- Gate Types, Gate Delays. |
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| 2 | Behavioral Modeling - Structured Procedures, Procedural Assignments, Timing Controls, Conditional Statements, Multiway Branching, Loops, Sequential and Parallel Blocks, Tasks and Functions – Exercises. FSM based HDL design-Moore & Mealy machines. |
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| 3 | Useful modeling techniques- Procedural continuous assignments, overriding parameters, conditional compilation and execution, time scales, useful system tasks, Advance Verilog Topics- Timing and delays – types of delay models, path delay modeling, Timing checks, delay back-annotation, Switch level modeling – switch modeling elements, examples. | |
| 4 | Logic Synthesis with Verilog HDL- What is logic synthesis, impact of logic synthesis, Verilog hdl synthesis, synthesis design flow, RTL to gates (Example, Verification of gate level net list, modeling tips for logic synthesis, examples of sequential circuit synthesis. | |
