Syllabus
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Course Code: MCA-20-31 Course Name: Computer Architecture and Parallel Processing |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Computational Model: Basic computational models, evolution and interpretation of computer architecture, concept of computer architecture as a multilevel hierarchical framework. Classification of parallel architectures, Relationships between programming languages and parallel architectures. Parallel Processing: Types and levels of parallelism, Instruction Level Parallel (ILP) processors, dependencies between instructions, principle and general structure of pipelines, performance measures of pipeline, pipelined processing of integer, Boolean, load and store instructions, VLIW architecture, Code Scheduling for ILP- Processors - Basic block scheduling, loop scheduling, global scheduling. |
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| 2 | Superscalar Processors: Emergence of superscalar processors, Tasks of superscalar processing – parallel decoding, superscalar instruction issue, shelving, register renaming, parallel execution, preserving sequential consistency of instruction execution and exception processing, comparison of VLIW & superscalar processors Branch Handling: Branch problem, Approaches to branch handling – delayed branching, branch detection and prediction schemes, branch penalties and schemes to reduce them, multiway branches, guarded execution. |
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| 3 | MIMD Architectures: Concepts of distributed and shared memory MIMD architectures, UMA, NUMA, CC-NUMA & COMA models, problems of scalable computers. Direct Interconnection Networks: Linear array, ring, chordal rings, star, tree, 2D mesh, barrel shifter, hypercubes. |
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| 4 | Dynamic interconnection networks: single shared buses, comparison of bandwidths of locked, pended & split transaction buses, arbiter logics, crossbar, multistage networks – omega, butterfly Cache coherence problem, hardware based protocols – snoopy cache protocol, directory schemes, and hierarchical cache coherence protocols. |
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