Syllabus
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Course Code: MT-CSE-20-14 Course Name: Elective- II - (i) Advanced Computer Architecture |
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| MODULE NO / UNIT | COURSE SYLLABUS CONTENTS OF MODULE | NOTES |
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| 1 | Instruction Level Parallelism (ILP): Data dependences and hazards – data dependences, control dependences; Basic Compiler Techniques for Exposing ILP – basic pipeline scheduling and loop unrolling, reducing branch costs with advanced branch prediction, overcoming data hazardous with dynamic scheduling, Tomasulo’s approach, hardware based speculation; Exploiting ILP using Multiple issue and Static Scheduling – VLIW & Superscalar processors, Advanced techniques for Instruction Delivery and Speculation; Limitations of ILP. | |
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Data Level Parallelism in Vector, SIMD & GPU Architectures: Vector Architecture – working of vector processors, vector execution time, multiple lanes, vector registers, memory banks, stride, gather-scatter; SIMD Instruction Set Extensions for Multimedia; Graphics Processing Units, Vector architecture vs. GPUs, Multimedia SIMD v/s GPUs; detecting and enhancing Loop-Level Parallelism – finding dependences, eliminating dependent computations Thread-Level Parallel Parallelism: Multiprocessor Architecture – centralized shared-memory architectures, cache coherence problem, schemes enforcing coherence, snooping coherence protocol; Extensions to basic coherence protocol; Distributed Shared-Memory and Directory-Based Coherence. |
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| 3 | Warehouse-Scale Computers (WSC) to Exploit Request-Level and Data-Level Parallelism: Programming models and workloads for WSC, architecture of warehouse-scale computers, physical infrastructure and costs of WSC; Cloud Computing. Memory Hierarchy: Cache performance – average memory access time & processor performance, miss penalty and out-of-order execution processors, cache optimizations; Virtual Memory – fast address translation, selecting page size, protection of virtual memory. |
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| 4 | MIMD Architectures: Architectural concepts of Distributed & Shared Memory MIMD architectures (UMA, NUMA, COMA, CC-NUMA); Interconnection Networks – direct interconnection networks (Linear Array, Ring, Star, 2D Mesh, Hyper cubes), switching techniques; dynamic interconnection networks (shared bus, crossbar, multistage networks); Specifications of top three super computers of Top500 list. | |
